Some of today's audio systems are developed for embedded processing in devices such as set-top boxes, digital versatile disk (DVD) players, camcorders, portable audio players, and so on. All of these systems rely on low-cost hardware decoders or low-cost digital signal processors (DSP). A major factor that affects the cost of any audio processing system is memory demands such as memory bandwidth. In simple audio-only applications, for example, there may be minimal memory consumption requirements, and in high-end set-top boxes, for example, there is a need for a large number of different functions to share memory bandwidth and share memory space. Optimizing the usage of memory space and memory bandwidth often results in large system cost savings. Savings in memory bandwidth may further be improved by incorporating improvements to audio bit stream syntax definition, and improvements to audio decoder architectures. Working with real limits of memory is critical, since as dynamic random access memory (DRAM) speeds rise, there is a corresponding increase in DRAM response time. RAS and CAS signals overhead, page break delays, and/or physical timing constraints of dual data rate RAM (DDR) systems may cause increased delay in the response time of DRAM devices. Although there is a simultaneous increase in the speeds of DRAMs, which results in larger amounts of DRAM data, the resulting DRAM data is very bursty in nature. It is desirable to have DRAMs with much longer burst periods, separated by longer access data delays.
For example, today's DDR technologies require a minimum burst length of 2 words. On a system bus width of 32 bits, this results in a minimum burst size of 8 bytes. Better bandwidth efficiency may be achieved by designing with a burst length of 4, since this may allow command functions to occupy the bus during DRAM burst accesses. A burst length of 4 would result in a burst of 16 bytes. Additional efficiency may be gained by increasing the burst size, since the RAS and page break overhead is usually 8 cycles. To achieve 50% efficiency would require a burst length of, for example, 16, or 64 bytes. To achieve an efficiency of 75% would require a burst length of 48, which would return 192 bytes. High-end systems such as processing systems with high functionality will require very high DRAM efficiency, which may be achieved through much longer burst lengths.
When coupled with real-time systems having a plurality of clients, each client must have the capability to take turns in accessing the DRAM resources. In such real-time systems having a plurality of clients, the clients are required to request more data to process, in order that the client may adequately tolerate the wait time consumed by other clients in the system. This also increases the burst size demanded by clients such as audio processing clients. However, this does not work well with certain types of audio syntax, audio systems, and/or audio decoder operations.
Furthermore, today's modern CPU architectures rely heavily on cache based subsystems. The CPU cache typically requests data from memory only as it is needed. As a result, the CPU must often wait for a period of time starting from a time instant when the request is made and ending a time instant when the data is returned from memory. Accordingly, this does not provide an optimal manner for processing.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.